The documentation and process conversion
measures necessary to comply with this revision
shall be completed by 14 April 2002.
INCH-POUND
MIL-PRF-19500/558D
14 January 2002
SUPERSEDING
MIL-PRF-19500/558C
31 August 1998
PERFORMANCE SPECIFICATION
SEMICONDUCTOR DEVICE, FOUR TRANSISTOR ARRAY,UNITIZED,
PNP, SILICON, SWITCHING TYPES 2N6987, 2N6987U, AND 2N6988,
JAN, JANTX, JANTXV, AND JANS
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for PNP, silicon, switching transistors, four
independent chip array. Four levels of product assurance are provided for each device type as specified in
MIL-PRF-19500.
1.2 Physical dimensions . See figures 1, 2, 3, and 4 (14-pin dual-in-line, 14-pin flat-pack, and 20-pin leadless
chip carrier) and 3.4.
1.3 Maximum ratings. (1)
P
T
T
A
= +25擄C (2)
W
2N6987
2N6987U
2N6988
1.5
1.0
0.4
V
CBO
(3)
V
EBO
(3)
V
CEO
(3)
I
C
(3)
T
OP
and T
STG
V dc
60
60
60
V dc
5
5
5
V dc
60
60
60
mA dc
600
600
600
擄C
-65 to +200
-65 to +200
-65 to +200
*
(1) Maximum voltage between transistors shall be
鈮?/div>
500 V dc.
(2) Derate linearly 8.57 mW/擄C above T
A
= +25擄C for 2N6987 and 5.71 mW/擄C for 2N6987U.
Derate linearly 2.286 mW/擄C above T
A
= +25擄C for 2N6988. Ratings apply to total package.
(3) Ratings apply to each transistor in the array.
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving
this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC, P. O. Box 3990,
Columbus, OH 43216- 5000, by using Standardization Document Improvement Proposal (DD Form 1426) appearing at
the end of the document or by letter.
AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
FSC 5961
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