IW4042B
Q
UAD
C
LOCKED
蘆D祿 L
ATCH
High-Voltage Silicon-Gate CMOS
CD4042B types contain four latch circuits, each strobed by a
common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p-channel output
devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are
present. When a CLOCK transition occurs (positive for
POLARITY = 0 and negative for POLARTY = 1) the information
present at the input during the CLOCK transition is retained at
ORDERING INFORMATION
the outputs until an opposite CLOCK transition occurs.
IW4042BN Plastic
The CD4042B types are supplied in 16-lead hermetic dual-in-
IW4042BD SOIC
line ceramic packages (D and F suffixes); 16-lead dual-in-line
T
A
= -55擄 to 125擄 C for all
plastic package (E suffix), and in chip form (H suffix).
packages
鈥?/div>
Operating Voltage Range: 3.0 to 18 V
鈥?/div>
Maximum input current of 1
碌A(chǔ)
at 18 V over full package-
temperature range; 100 nA at 18 V and 25擄C
鈥?/div>
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
PIN ASSIGNMENT
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
Q4
1
16
VCC
Q1
Q1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Q4
D4
D3
Q3
Q3
Q2
Q2
LOGIC DIAGRAM
D1
CLOCK
POLARITY
D2
GND
PIN 16 =V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Clock
Polarity
Q
0
0
D
1
0
Latch
1
1
D
0
1
Latch
1
1
2
3
4
5
