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ISPLSI3320-100LB320 Datasheet

  • ISPLSI3320-100LB320

  • 16頁

  • ETC

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ispLSI 3320
廬
In-System Programmable High Density PLD
Features
鈥?HIGH-DENSITY PROGRAMMABLE LOGIC
鈥?160 I/O Pins
鈥?14000 PLD Gates
鈥?480 Registers
鈥?High Speed Global Interconnect
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?HIGH-PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 100 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 10 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?Unused Product Term Shutdown Saves Power
鈥?ispLSI FEATURES:
鈥?5V In-System Programmable (ISP鈩? Using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Debugging
鈥?100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
A0
A1
A2
A3
B0
B1
B2
B3
Functional Block Diagram
Output Routing Pool (ORP)
Boundary
Scan
G3
G2
G1
G0
Output Routing Pool (ORP)
F3
F2
F1
F0
Output Routing Pool (ORP)
H0
D Q
E3
H1
H2
D Q
OR
Array
AND Array
D Q
E2
E1
D Q
H3
D Q
Twin
GLB
E0
Output Routing Pool (ORP)
I0
OR
Array
D3
D Q
I1
I2
D2
D Q
D1
I3
D0
Output Routing Pool (ORP)
J0
C3
J1
J2
Global Routing Pool
(GRP)
C2
C1
J3
C0
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Enhanced Pin Locking Capability
鈥?Five Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to
Minimize Switching Noise
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?Pin Compatible with ispLSI 3160
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0139/3320
Description
The ispLSI 3320 is a High-Density Programmable Logic
Device containing 480 Registers, 160 Universal I/O pins,
five Dedicated Clock Input Pins, ten Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3320 features 5V in-system pro-
grammability and in-system diagnostic capabilities. The
ispLSI 3320 offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3320 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...J3.
There are a total of 40 of these Twin GLBs in the ispLSI
3320 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
Copyright 漏 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 1999
3320_06
1
Output Routing Pool (ORP)
Output Routing Pool (ORP)
D Q
Output Routing Pool (ORP)

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