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ISPLSI2128V-80LQ160I Datasheet

  • ISPLSI2128V-80LQ160I

  • 3.3V High Density Programmable Logic

  • 15頁

  • LATTICE   LATTICE

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ispLSI 2128V
3.3V High Density Programmable Logic
Features
鈥?HIGH DENSITY PROGRAMMABLE LOGIC
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
6000 PLD Gates
128 and 64 I/O Pin Versions, Eight Dedicated Inputs
128 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
Output Routing Pool (ORP)
D7
D6
D5
D4
Output Routing Pool (ORP)
D3
D2
D1
D0
C7
廬
Functional Block Diagram*
Output Routing Pool (ORP)
A0
A1
C6
A2
D
Q
C5
鈥?3.3V LOW VOLTAGE 2128 ARCHITECTURE
鈥?Interfaces with Standard 5V TTL Devices
鈥?The 128 I/O Pin Version is Fuse Map Compatible
with 5V ispLSI 2128
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A3
ES
IG
D
Q
D
Q
C4
Output Routing Pool (ORP)
A4
GLB
C3
A5
C2
A7
EW
f
max
= 80 MHz Maximum Operating Frequency
t
pd
= 10 ns Propagation Delay
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
A6
D
B0
B1
B2
B3
B4
Output Routing Pool (ORP)
D
Q
C1
Global Routing Pool (GRP)
B5
B6
B7
C0
Output Routing Pool (ORP)
*128 I/O Version Shown
N
CLK 0
CLK 1
CLK 2
0139A/2128V
鈥?THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
21
28
VE
鈥?3.3V In-System Programmability (ISP鈩? Using
Boundary Scan Test Access Port (TAP)
鈥?Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
U
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
pL
SI
FO
The ispLSI 2128V is a High Density Programmable Logic
Device available in 128 and 64 I/O-pin versions. The
device contains 128 Registers, eight Dedicated Input
pins, three Dedicated Clock Input pins, two dedicated
Global OE input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 2128V features in-
system programmability through the Boundary Scan
Test Access Port (TAP). The ispLSI 2128V offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2128V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
R
鈥?IN-SYSTEM PROGRAMMABLE
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2128v_14
1
Output Routing Pool (ORP)
Logic
Array
Output Routing Pool (ORP)
N
S

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