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ISPLSI2064A-80LT100I Datasheet

  • ISPLSI2064A-80LT100I

  • Electrically-Erasable Complex PLD

  • 13頁(yè)

  • ETC

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ispLSI 2064/A
In-System Programmable High Density PLD
Features
鈥?ENHANCEMENTS
鈥?ispLSI 2064A is Fully Form and Function Compatible
to the ispLSI 2064, with Identical Timing
Specifcations and Packaging
鈥?ispLSI 2064A is Built on an Advanced 0.35 Micron
E
2
CMOS
廬
Technology
Output Routing Pool (ORP)
Input Bus
廬
Functional Block Diagram
Output Routing Pool (ORP)
B7
B6
B5
B4
鈥?2000 PLD Gates
鈥?64 I/O Pins, Four Dedicated Inputs
鈥?64 Registers
鈥?High Speed Global Interconnect
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 125 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 7.5 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?Unused Product Term Shutdown Saves Power
鈥?IN-SYSTEM PROGRAMMABLE
鈥?In-System Programmable (ISP鈩? 5V Only
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Enhanced Pin Locking Capability
鈥?Three Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to
Minimize Switching Noise
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Input Bus
A2
GLB
Logic
Array
D Q
D Q
B1
D Q
A3
A4
A5
A6
A7
B0
Output Routing Pool (ORP)
Input Bus
Fu
Description
0139Bisp/2064
The ispLSI 2064 and 2064A are High Density Program-
mable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The 2064 and 2064A feature 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 2064 and 2064A offer non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1鈥7
(Figure 1). There are a total of 16 GLBs in the ispLSI 2064
and 2064A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
April 2000
2064_07
1
Input Bus
A1
D Q
B2
Output Routing Pool (ORP)
鈥?HIGH DENSITY PROGRAMMABLE LOGIC
A0
Global Routing Pool
(GRP)
B3

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