The ispLSI 2032V is a High Density Programmable Logic
Device that can be used in both 3.3V and 5V systems.
The device contains 32 Registers, 32 Universal I/O pins,
two Dedicated Input Pins, three Dedicated Clock Input
Pins, one dedicated Global OE input pin and a Global
Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2032V features in-system programmability through
the Boundary Scan Test Access Port (TAP). The ispLSI
2032V offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2032V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
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Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
U
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
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