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ISPLSI1048-50LQI Datasheet

  • ISPLSI1048-50LQI

  • Electrically-Erasable Complex PLD

  • 123.04KB

  • 12頁

  • ETC

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ispLSI 1048
廬
In-System Programmable High Density PLD
Features
鈥?HIGH-DENSITY PROGRAMMABLE LOGIC
鈥?8000 PLD Gates
鈥?96 I/O Pins, Ten Dedicated Inputs
鈥?288 Registers
鈥?High-Speed Global Interconnects
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?Security Cell Prevents Unauthorized Copying
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 80 MHz Maximum Operating Frequency
鈥?/div>
f
max
= 50 MHz for Industrial Devices
鈥?/div>
t
pd
= 15 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile E
2
CMOS Technology
鈥?100% Tested
鈥?IN-SYSTEM PROGRAMMABLE
鈥?In-System Programmable鈩?(ISP鈩? 5-Volt Only
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Debugging
鈥?COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Four Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
A0
Output Routing Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
D7
D5
Output Routing Pool
D Q
A1
A2
A3
A4
A5
A6
A7
D6
Logic
D Q
U
SE
C
O is
M p
M L
ER SI
C 10
IA 4
D L 8E
ES & A
IG IN F
N D OR
S U
ST N
EW
R
IA
L
D Q
D Q
Global Routing Pool (GRP)
Array
GLB
D4
D3
D2
D1
D0
CLK
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
Description
The ispLSI 1048 is a High-Density Programmable Logic
Device which contain 288 Registers, 96 Universal I/O
pins, ten Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1048 devices is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see figure 1). There are a total of 48 GLBs in the
ispLSI 1048 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright 漏 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
1048_06
1

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