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ISPGAL22V10B-15LJ Datasheet

  • ISPGAL22V10B-15LJ

  • In-System Programmable E2CMOS PLD

  • 247.68KB

  • 15頁

  • LATTICE   LATTICE

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Specifications
ispGAL22V10
ispGAL22V10
In-System Programmable E
2
CMOS PLD
Generic Array Logic鈩?/div>
FEATURES
鈥?IN-SYSTEM PROGRAMMABLE鈩?(5-V ONLY)
鈥?4-Wire Serial Programming Interface
鈥?Minimum 10,000 Program/Erase Cycles
鈥?Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?7.5 ns Maximum Propagation Delay
鈥?Fmax = 111 MHz
鈥?5 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
鈥?COMPATIBLE WITH STANDARD 22V10 DEVICES
鈥?Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
鈥?E
2
CELL TECHNOLOGY
鈥?In-System Programmable Logic
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?TEN OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Software-Driven Hardware Configuration
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PIN CONFIGURATION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
2
) floating gate technology to provide the industry's
first in-system programmable 22V10 device. E
2
technology of-
fers high speed (<100ms) erase times, providing the ability to re-
program or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
I
I
I
MODE
I
I
I
11 12
14
16
18 19
7
5
FUNCTIONAL BLOCK DIAGRAM
RESET
I/CLK
8
OLMC
I/O/Q
I
10
I
12
OLMC
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I
14
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I
I/O/Q
12
I
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
SDO
SDI
MODE
SCLK
PROGRAMMING
LOGIC
8
OLMC
I/O/Q
PRESET
PLCC
I/CLK
SCLK
I/O/Q
I/O/Q
I
I
Vcc
SSOP
4
2
28
26
25
I/O/Q
I/O/Q
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1
28
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
ispGAL22V10
Top View
23
I/O/Q
SDO
7
ispGAL
22V10
22
Top View
9
21
I/O/Q
I/O/Q
I/O/Q
14
15
I
I
GND
SDI
I
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
isp22v10_02
1

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