QLogic Corporation
ISP2100A Intelligent Fibre Channel Processors
Data Sheet
Features
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Available in two versions:
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66-MHz, 64-bit PCI host bus interface
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33-MHz, 64-bit PCI host bus interface
Compliance with
PCI Local Bus Speci鏗乧ation
revision 2.1
Compliance with ANSI SCSI standard
X3.131-1994
Supports all Fibre Channel topologies and classes
of service
Compliance with
Fibre Channel Arbitrated Loop
(FC-AL) Direct Disk Attach Pro鏗乴e
and
Fibre
Channel Public Loop (FC-PL) Fabric Loop Attach
Pro鏗乴e,
class 2 and class 3 service
Compliance with
PCI Bus Power Management
Interface Speci鏗乧ation
Revision 1.0 (PC97)
ISP2100A
PCI INTERFACE
RECEIVE DATA
DMA CHANNEL
RECEIVE FRAME
BUFFER
PCI
ADDRESS/DATA
64-BIT, 66-MHZ
BUS
FRAME BUFFER
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Supports 100 Mbytes/sec sustained Fibre Channel
data transfer rate
Initiator or target mode
Onboard RISC processor to execute operations at
the I/O control-block (IOCB) level from the host
memory
Onboard gigabit serial transceivers
Supports external transceivers with a
10-bit interface
Supports PCI dual-address cycle (64-bit
addressing) and cache commands
No host intervention required to execute SCSI
operations from start to 鏗乶ish
Simultaneous, multiple logical threads
Full duplex frame buffer architecture
Supports JTAG boundary scan
FIBRE ENGINE
FIBRE
CHANNEL
GIGABIT
SERIAL
RECEIVER
2
LOOP
IN
10
EXT.
TRANS-
CEIVER
LOOP
IN
LOOP
OUT
GIGABIT
SERIAL
TRANSMITTER
2
LOOP
OUT
RECEIVE
PATH
TRANSMIT DATA
DMA CHANNEL
TRANSMIT FRAME
BUFFER
TRANSMIT
PATH
10
PCI
CONTROL
COMMAND
DMA
CHANNEL
MAILBOX
REGISTERS
CONTROL/
CONFIGURATION
REGISTERS
F
I
F
O
I/O BUS
RISC
REGISTER
FILE
BOOT
CODE
MEM.
I/F
CONTROL
REGISTERS
ALU
ADDRESS
NVRAM
FLASH
BIOS
DATA
EXTERNAL
CODE/DATA
MEMORY
Figure 1. ISP2100A Block Diagram
83210-580-01 B
ISP2100A
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