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ISP1761ET Datasheet

  • ISP1761ET

  • Hi-Speed Universal Serial Bus On-The-Go controller

  • 689.88KB

  • 158頁

  • PHILIPS

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ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 01 鈥?12 January 2005
Product data sheet
1. General description
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)
Controller integrated with the advanced Philips Slave Host Controller and the Philips
ISP1582 Peripheral Controller.
The Hi-Speed USB Host Controller and Peripheral Controller comply to
Universal Serial
Bus Speci鏗乧ation Rev. 2.0
and support data transfer speeds of up to 480 Mbit/s. The
Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is
adapted from
Enhanced Host Controller Interface Speci鏗乧ation for Universal Serial Bus
Rev. 1.0.
The OTG controller is compliant with
On-The-Go Supplement to the USB
Speci鏗乧ation Rev. 1.0a.
The ISP1761 has three USB ports. Port 1 can be con鏗乬ured to function as a downstream
port, an upstream port or an OTG port; ports 2 and 3 are always con鏗乬ured as
downstream ports. The OTG port can switch its role from host to peripheral, and
peripheral to host. The OTG port can become a host through the Host Negotiation
Protocol (HNP) as speci鏗乪d in the OTG supplement.
2. Features
s
Compliant with
Universal Serial Bus Speci鏗乧ation Rev. 2.0;
supporting data transfer at
high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
s
Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)
peripheral support
s
Three USB ports that support three operational modes:
x
Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller
ports
x
Mode 2: Ports 1, 2 and 3 are Host Controller ports
x
Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller
ports
s
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
s
Multitasking support with Virtual Segmentation feature (up to four banks)
s
High-speed memory controller (variable latency and SRAM external interface)
s
Directly addressable memory architecture
s
Generic processor interface to most CPUs, such as: Hitachi
廬
SH-3 and SH-4, Philips
XA, Intel
廬
StrongARM
廬
, NEC
廬
and Toshiba
廬
MIPS, Motorola
廬
DragonBall鈩?and
PowerPC
廬
Reduced Instruction Set Computer (RISC) processors
s
Con鏗乬urable 32-bit and 16-bit external memory data bus
s
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
s
Slave DMA implementation on CPU interface for reducing the host system鈥檚 CPU load

ISP1761ET 產(chǎn)品屬性

  • NXP

  • USB 接口集成電路

  • 1.65 V to 3.6 V

  • Reel

  • 1300

  • ISP1761ET,557

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