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ISP1181DGG Datasheet

  • ISP1181DGG

  • Full-speed Universal Serial Bus interface device

  • 69頁(yè)

  • PHILIPS

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ISP1181
Full-speed Universal Serial Bus interface device
Rev. 01 鈥?13 March 2000
Objective speci鏗乧ation
1. General description
The ISP1181 is a Universal Serial Bus (USB) interface device which complies with
Universal Serial Bus Speci鏗乧ation Rev. 1.1.
It provides full-speed USB
communication capacity to microcontroller or microprocessor-based systems. The
ISP1181 communicates with the system鈥檚 microcontroller or microprocessor through
a high-speed general-purpose parallel interface.
The fully autonomous Direct Memory Access (DMA) operation - auto download, auto
repeat, auto execution - removes the need for the device to re-enable or re-initialize
the DMA operation every time.
The modular approach to implementing a USB interface device allows the designer to
select the optimum system microcontroller from the wide variety available. The ability
to re-use existing architecture and 鏗乺mware investments shortens development time,
eliminates risks and reduces costs. The result is fast and ef鏗乧ient development of the
most cost-effective USB peripheral solution.
The ISP1181 is ideally suited for application in many personal computer peripherals,
such as printers, scanners, external mass storage (zip drive) devices and digital still
cameras. It offers an immediate cost reduction for applications that currently use
SCSI implementations.
c
c
2. Features
s
Complies with
Universal Serial Bus Speci鏗乧ation Rev. 1.1
and most Device Class
speci鏗乧ations
s
High performance USB interface device with integrated Serial Interface Engine
(SIE), FIFO memory, transceiver and 3.3 V voltage regulator
s
Interrupt endpoint can be con鏗乬ured in 鈥榬ate feedback鈥?mode
s
High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface
s
Fully autonomous and multi-con鏗乬uration DMA operation
s
Up to 14 programmable USB endpoints with 2 鏗亁ed control IN/OUT endpoints
s
Integrated physical 2462 bytes of multi-con鏗乬uration FIFO memory
s
Endpoints with double buffering to increase throughput and ease real-time data
transfer
s
Seamless interface with most microcontrollers/microprocessors
s
Bus-powered capability with low power consumption and low 鈥榮uspend鈥?current
s
6 MHz crystal oscillator with integrated PLL for low EMI

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