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IS93C76A-2GRI Datasheet

  • IS93C76A-2GRI

  • 8K-BIT/16K-BIT SERIAL ELECTRICALLY ERASABLE PROM

  • 13頁

  • ISSI   ISSI

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IS93C76A
IS93C86A
ISSI
Preliminary Information
MAY 2005
廬
8K-BIT/16K-BIT SERIAL ELECTRICALLY
ERASABLE PROM
FEATURES
鈥?Industry-standard Microwire Interface
鈥?Non-volatile data storage
鈥?Low voltage operation:
Vcc = 1.8V to 5.5V -2
Vcc = 2.5V to 5.5V -3
鈥?Full TTL compatible inputs and outputs
鈥?Auto increment for efficient data dump
鈥?User Configured Memory Organization
鈥?By 16-bit or by 8-bit
鈥?Hardware and software write protection
鈥?Defaults to write-disabled state at power-up
鈥?Software instructions for write-enable/disable
鈥?Enhanced low voltage CMOS E
2
PROM
technology
鈥?Versatile, easy-to-use Interface
鈥?Self-timed programming cycle
鈥?Automatic erase-before-write
鈥?Programming status indicator
鈥?Word and chip erasable
鈥?Chip select enables power savings
鈥?Durable and reliable
鈥?40-year data retention after 1M write cycles
鈥?1 million write cycles
鈥?Unlimited read cycles
鈥?Schmitt-trigger Inputs
鈥?Industrial and Automotive Temperature Grade
鈥?Lead-free available
DESCRIPTION
IS93C76A/86A are 8kb/16kb non-volatile, ISSI
廬
serial EEPROMs. They are fabricated using an
enhanced CMOS design and process. IS93C76A/
86A contains power-efficient read/write memory,
and organization of either 1,024/2,048 bytes of 8
bits or 512/1,024 words of 16 bits. When the
ORG pin is connected to Vcc or left unconnected,
x16 is selected; when it is connected to ground,
x8 is selected.
An instruction set defines the operation of the
devices, including read, write, and mode-enable
functions. To protect against inadvertent data
modification, all erase and write instructions are
accepted only while the device are write-enabled.
A selected x8 byte or x16 word can be modified
with a single WRITE or ERASE instruction.
Additionally, the two instructions WRITE ALL or
ERASE ALL can program an entire array. Once a
device begins its self-timed program procedure,
the data out pin (Dout) can indicate the READY/
BUSY
status by raising chip select (CS). The self-
timed write cycle includes an automatic erase-
before-write capability. The devices can output
any number of consecutive bytes/words using a
single READ instruction.
FUNCTIONAL BLOCK DIAGRAM
DATA
REGISTER
D
IN
INSTRUCTION
REGISTER
INSTRUCTION
DECODE,
CONTROL,
AND
CLOCK
GENERATION
ADDRESS
REGISTER
DUMMY
BIT
R/W
AMPS
ADDRESS
DECODER
EEPROM
ARRAY
1024/2048x8
512/1024x16
D
OUT
CS
SK
WRITE
ENABLE
HIGH VOLTAGE
GENERATOR
Copyright 漏 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. 鈥?www.issi.com 鈥?/div>
1-800-379-4774
Rev. 00F
05/26/05
1

IS93C76A-2GRI 產(chǎn)品屬性

  • ISSI

  • 電可擦除可編程只讀存儲器

  • 8 Kbit

  • 1024 K x 8

  • 40 yr

  • 1 MHz

  • 3 mA

  • 1.8 V, 5.5 V

  • + 85 C

  • SMD/SMT

  • SOIC-8

  • 5 ms

  • 2-Wire

  • - 40 C

  • Tube

  • 100

  • 5.5 V

  • 1.8 V

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