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IS62VV25616LL-70M Datasheet

  • IS62VV25616LL-70M

  • x16 SRAM

  • 10頁

  • ETC

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IS62VV25616LL
256K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
鈥?High-speed access time: 70, 85, ns
鈥?CMOS low power operation
鈥?36 mW (typical) operating
鈥?9 碌W (typical) CMOS standby
鈥?Single 1.7V-1.95V V
CC
power supply
鈥?Fully static operation: no clock or refresh
required
鈥?Three state outputs
鈥?Data control for upper and lower bytes
鈥?Industrial temperature available
鈥?Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (7.2mm x 8.7mm)
ISSI
NOVEMBER 2001
廬
DESCRIPTION
The
ISSI
IS62VV25616LL is a high-speed, 4,194,304 bit
static RAMs organized as 262,144 words by 16 bits. They
are fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
For the IS62VV25616LL, when
CE
is HIGH (deselected)
or
CE
is low and both
LB
and
UB
are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62VV25616LL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA (7.2mm x 8.7mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. 漏 Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. A
11/01/01
1

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