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IS62LV12816LL-55BI Datasheet

  • IS62LV12816LL-55BI

  • x16 SRAM

  • 114.08KB

  • 10頁

  • ETC

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IS62LV12816LL
128K x 16 CMOS STATIC RAM
FEATURES
鈥?High-speed access time: 55, 70, 100 ns
鈥?CMOS low power operation
鈥?120 mW (typical) operating
鈥?6 碌W (typical) CMOS standby
鈥?TTL compatible interface levels
鈥?Single 2.5V-3.45V V
CC
power supply
鈥?Fully static operation: no clock or refresh
required
鈥?Three state outputs
鈥?Data control for upper and lower bytes
鈥?Industrial temperature available
鈥?Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (6mm x 8mm)
ISSI
DESCRIPTION
廬
NOVEMBER 2000
The
ISSI
IS62LV12816LL is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62LV12816LL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA. (6mm x 8mm)
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. 漏 Copyright 2000, Integrated Silicon Solution, Inc.
CONTROL
CIRCUIT
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. D
12/15/00
1

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