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IS61LV25616-8TI Datasheet

  • IS61LV25616-8TI

  • 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V ...

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  • ISSI   ISSI

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IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
鈥?High-speed access time:
鈥?7, 8, 10, 12, and 15 ns
鈥?CMOS low power operation
鈥?Low stand-by power:
鈥?Less than 5 m
A
(typ.) CMOS stand-by
鈥?TTL compatible interface levels
鈥?Single 3.3V power supply
鈥?Fully static operation: no clock or refresh
required
鈥?Three state outputs
鈥?Data control for upper and lower bytes
鈥?Industrial temperature available
ISSI
廬
AUGUST 2000
DESCRIPTION
The
ISSI
IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design tech-
niques, yields high-performance and low power consumption
devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. 漏 Copyright 2000, Integrated Silicon Solution, Inc.
CONTROL
CIRCUIT
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. B
09/29/00
1

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