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IS61LV12824-9TQ Datasheet

  • IS61LV12824-9TQ

  • x24 SRAM

  • 80.88KB

  • 11頁

  • ETC

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IS61LV12824
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
鈥?High-speed access time: 8, 9, 10, 12 ns
鈥?CMOS low power operation
鈥?756 mW (max.) operating @ 8 ns
鈥?36 mW (max.) standby @ 8 ns
鈥?TTL compatible interface levels
鈥?Single 3.3V power supply
鈥?Fully static operation: no clock or refresh
required
鈥?Three state outputs
鈥?Available in 119-pin Plastic Ball Grid Array
(PBGA) and 100-pin TQFP packages.
鈥?Industrial temperature available
ISSI
廬
DECEMBER 1999
DESCRIPTION
The
ISSI
IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When
CE1, CE2
are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE1,
CE2,
CE2
and
OE.
The active
LOW Write Enable (WE) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 24
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O23
COLUMN I/O
CE2
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. 漏 Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. B
04/17/01
1

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