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IS61C64B-10N Datasheet

  • IS61C64B-10N

  • x8 SRAM

  • 7頁

  • ETC

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IS61C64B
8K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
鈥?High-speed access time: 10, 12, and 15 ns
鈥?Automatic power-down when chip is
deselected
鈥?CMOS low power operation
鈥?450 mW (typical) operating
鈥?250 碌W (typical) standby
鈥?TTL compatible interface levels
鈥?Single 5V power supply
鈥?Fully static operation: no clock or refresh
required
鈥?Three state outputs
鈥?One Chip Enables (CE) for increased speed
ISSI
廬
JULY 2001
DESCRIPTION
The
ISSI
IS61C64B is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 10 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 碌W (typical) with CMOS input levels.
Easy memory expansion is provided by using one Chip
Enable input,
CE.
The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS61C64B is packaged in the JEDEC standard 28-pin,
300-mil DIP and SOJ, and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
DECODER
256 X 256
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. 漏 Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. C
07/17/01
1

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