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IS42S16100

ISSI

DESCRIPTION

廬

512K Words x 16 Bits x 2 Banks (16-MBIT)

SYNCHRONOUS DYNAMIC RAM

FEATURES

鈥?Clock frequency: 166, 143, 100 MHz

鈥?Fully synchronous; all signals referenced to a

positive clock edge

鈥?Two banks can be operated simultaneously

and independently

鈥?Dual internal bank controlled by A11 (bank

select)

鈥?Single 3.3V power supply

鈥?LVTTL interface

鈥?Programmable burst length

鈥?(1, 2, 4, 8, full page)

鈥?Programmable burst sequence:

Sequential/Interleave

鈥?Auto refresh, self refresh

鈥?4096 refresh cycles every 128 ms

鈥?Random column address every clock cycle

鈥?Programmable

CAS

latency (2, 3 clocks)

鈥?Burst read/write and burst read/single write

operations capability

鈥?Burst termination by burst stop and precharge

command

鈥?Byte controlled by LDQM and UDQM

鈥?Package 400-mil 50-pin TSOP II

NOVEMBER

2001

ISSI

's 16Mb Synchronous DRAM IS42S16100 is organized

as a 524,288-word x 16-bit x 2-bank for improved

performance. The synchronous DRAMs achieve high-speed

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

PIN CONFIGURATIONS

50-Pin TSOP (Type II)

VCC

I/O0

I/O1

GNDQ

I/O2

I/O3

VCCQ

I/O4

I/O5

GNDQ

I/O6

I/O7

VCCQ

LDQM

WE

CAS

RAS

CS

A11

A10

A0

A1

A2

A3

VCC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

GND

I/O15

I/O14

GNDQ

I/O13

I/O12

VCCQ

I/O11

I/O10

GNDQ

I/O9

I/O8

VCCQ

NC

UDQM

CLK

CKE

NC

A9

A8

A7

A6

A5

A4

GND

PIN DESCRIPTIONS

A0-A11

A0-A10

A11

A0-A7

I/O0 to I/O15

CLK

CKE

CS

RAS

Address Input

Row Address Input

Bank Select Address

Column Address Input

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Integrated Silicon Solution, Inc. 鈥?1-800-379-4774

Rev. C

11/01/01

1

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• IS42S16400...
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