IS41C4100
IS41LV4100
1Meg x 4 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
鈥?TTL compatible inputs and outputs
鈥?Refresh Interval: 1024 cycles/16 ms
鈥?Refresh Mode :
RAS-Only, CAS-before-RAS
(CBR), and Hidden
鈥?JEDEC standard pinout
鈥?Single power supply
5V 鹵 10% (IS41C4100)
3.3V 鹵 10% (IS41LV4100)
鈥?Industrail Temperature Range -40
o
C to 85
o
C
ISSI
DESCRIPTION
廬
PRELIMINARY INFORMATION
SEPTEMBER 2001
The
ISSI
IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access
EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as
short as 10ns per 4-bit word.
These features make the IS41C4100 and IS41LV4100 ideally
suited for high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C4100 and IS41LV4100 are available in a 20-pin,
300-mil SOJ package.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATION
20-Pin SOJ
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
20
19
18
17
16
GND
I/O3
I/O2
CAS
OE
PIN DESCRIPTIONS
A0-A9
I/O0-I/O3
WE
OE
RAS
CAS
V
CC
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
A0
A1
A2
A3
Vcc
6
7
8
9
10
15
14
13
12
11
A8
A7
A6
A5
A4
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. 漏 Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
PRELIMINARY INFORMATION
09/10/01
Rev. 00A
1