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IS41C16105-50T Datasheet

  • IS41C16105-50T

  • 1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

  • 18頁(yè)

  • ISSI   ISSI

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IS41C16105
IS41LV16105
1M x 16 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
鈥?TTL compatible inputs and outputs; tristate I/O
鈥?Refresh Interval:
鈥?1,024 cycles/16 ms
鈥?Refresh Mode:
鈥?/div>
RAS-Only, CAS-before-RAS
(CBR), and Hidden
鈥?JEDEC standard pinout
鈥?Single power supply:
鈥?5V 鹵 10% (IS41C16105)
鈥?3.3V 鹵 10% (IS41LV16105)
鈥?Byte Write and Byte Read operation via two
CAS
鈥?Extended Temperature Range -30
o
C to 85
o
C
鈥?Industrail Temperature Range -40
o
C to 85
o
C
ISSI
DESCRIPTION
廬
FEBRUARY 2000
The
ISSI
IS41C16105 and IS41LV16105 are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access Memo-
ries. Fast Page Mode allows 1,024 random accesses within a single
row with access cycle time as short as 20 ns per 16-bit word. The
Byte Write control, of upper and lower byte, makes the IS41C16105
ideal for use in 16-, 32-bit wide data bus systems.
These features make the IS41C16105 and IS41LV16105 ideally
suited for high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral applications.
The IS41C16105 and IS41LV16105 are packaged in a
42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATIONS
44(50)-Pin TSOP (Type II)
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. 漏 Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. A
03/03/00
1

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