IS24C16
IS24C16
16,384-BIT SERIAL ELECTRICALLY
ERASABLE PROM
ISSI
ADVANCE INFORMATION
OCTOBER 1997
ISSI
廬
廬
FEATURES
鈥?Low power CMOS
鈥?Active current less than 3.0 mA
鈥?Standby current less than 35
碌A(chǔ)
鈥?Hardware write protection
鈥?Write control pin
鈥?Internally organized as eight banks
鈥?256 pages x 8 bytes
鈥?Two-wire serial interface
鈥?Bidirectional data transfer protocol
鈥?Flexible byte write and 16-byte page-write
modes
鈥?High-reliability
鈥?Endurance: 100,000 cycles per byte
鈥?Data retention: 100 years
鈥?Automatic word address incrementing
鈥?Sequential register read
鈥?Filtered inputs for noise suppression
鈥?8-pin PDIP or SOIC packages
OVERVIEW
The IS24C16 is a low cost, low power, low voltage
serial EEPROM and organized as 2,048 x 8 bits. The
memory is configured as 128 pages of 16 bytes each. It is
fabricated using
ISSI
鈥檚 advanced CMOS EEPROM tech-
nology and operates from a single supply.
The IS24C16 is internally organized as a 256 x 8 memory
bank. The IS24C16 features a serial interface and soft-
ware protocol allowing operation on a simple 2-wire bus.
Included is a bidirectional serial data bus synchronized by
a clock offering flexible byte write and a faster 16-byte
page write. A write protect pin can protect data in the upper
quadrant of memory.
PIN CONFIGURATION
8-Pin DIP and SOIC
PIN DESCRIPTIONS
Serial Clock (SCL)
- The SCL input is used to clock all data
into and out of the device. In the WRITE mode, data must
remain stable when SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA)
- The SDA pin is a bidirectional pin used
to transfer data into and out of the device. Data may
change only when SCL is LOW. It is an open-drain output,
and may be wire-ORed with any number of open-drain or
open-collector outputs.
A0, A1, and A2:
These pins are not connected.
Write Control (
WC
)
- The Write Control input is used to
disable any attempt to write to the memory. When HIGH,
the upper half of array is protected against write opera-
tions; when LOW, the write function is normal. The part can
be read independent of the state of
WC
pin. When not
connected this pin will be pulled LOW.
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
PIN DESCRIPTIONS
A0-A2
SDA
SCL
Address Inputs (No connection)
Serial Data I/O
Serial Clock Input
Write Control Input
Power
Ground
WC
Vcc
GND
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. 漏 Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EE001-0C
10/03/97
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