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IQX160-7PQ208 Datasheet

  • IQX160-7PQ208

  • User Programmable Special Function ASIC

  • 65頁

  • ETC

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IQX Family Data Sheet
F
EATURES
鈥?/div>
SRAM-based, in-system programmable
鈥?/div>
Switch Matrix
鈥?Non-Blocking
鈥?Identical and predictable delays
鈥?One-to-one, one-to-many and many-to-one connections
鈥?/div>
RapidConfigure鈩?parallel interface for fast, incremental
configuration of Switch Matrix and I/O Port attributes
鈥?100% JTAG compliant
鈥?/div>
Clocked, Latched and Flow-through Dataflow Modes
鈥?As low as 7.5 ns pin-to-pin delay in flow-through mode
and 133 MHz clock rate in registered mode
鈥?/div>
I/O Ports
鈥?Individually programmable as input, output or
bidirectional
鈥?For each I/O Port, clock, clock enable, input enable and
output enable can be selected independently from a large
pool of common control signals
鈥?12 mA current drive
鈥?Separated I/O power pins for easy interfacing between
5V and 3.3V signals
D
ESCRIPTION
The IQX family of SRAM-based bit-oriented switching devices is
manufactured using a 0.6碌 m CMOS process. These devices
offer clock speeds of up to 133 MHz and pin-to-pin delay as low
as 7.5 ns.
The IQX devices are used in applications requiring dynamic
switching and flexible routing / interconnection of signals. These
applications include communication switches, network systems,
DSP / image processing engines and file/video servers.
At the heart of IQX devices is a non-blocking Switch Matrix. A
line in the Switch Matrix can be connected to one or more other
lines. The Switch Matrix lines are connected to I/O Ports with
programmable functional attributes.
The RapidConfigure parallel interface allows connections in the
Switch Matrix to be changed quickly and incrementally. This
interface can also be used to configure I/O Port attributes
individually and incrementally. In either case, data integrity is
maintained on all unchanged signal paths through the device.
The IQX devices support the industry standard JTAG (IEEE
1149.1) interface for boundary scan testing. The same interface
can also used for serially downloading the configuration bit
stream into the devices.
Dedicated
I/O Control Signals
Shared with
I/O Control
Signals
I/O Port
I/O Port
I/O Port
I/O Port
Signal
Ports
Switch Matrix
[Crossbar Array]
I/O
Control
I/O Port
Shared with
RapidConfigure
Interface Signals
I/O Port
I/O Port
RapidConfigure
Interface
JTAG Configuration Control
TDO TDI TMS TCK TRST*
Figure 1. IQX Functional Block Diagram
June 2000
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