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IMP16C552-IJ68 Datasheet

  • IMP16C552-IJ68

  • Dual Universal Asynchronous Receiver/Transmitter (UART) with...

  • 34頁(yè)

  • IMP

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IMP16C552
Data Communications
Dual Universal Asynchronous
Receiver/Transmitter (UART)
.
with 16-BYTE FIFO & Parallel Printer Port
Key Features
Two fully programmable serial 1/0
.
channels (DC TO 512K BAUD )
Tri-state TTL drive capabilities for
bi-directional data bus and control bus
on each channel
Loopback control for communications
link fault isolation for each UART
Line break generation and detection
for each UART
Complete status reporting capabilities
Generation and stripping of serial
asynchronous data control bits
(start ,stop parity )
Programmable baud rate generator
and modem control signals for each
channel
Fully prioritized independent interrupt
system controls for each channel
16byte FIFO buffers on both transmit
and receive of each channel to reduce
number of interrupts presented to the
CPU
Programmable FIFO threshold loves
of 1,4,8,or 14,bytes on each channel
Two modes of
DMA
signaling
available
for
transfer
of
data
characters to and from FIFO buffers
Fully
bi-directional
centronics
compatible parallel port direct printer
interface
Advanced
CMOS
low
power
technology with single +5voit supply
68-pin PLCC package
Pin
Configuration
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Rxrdy0*
RISD1*
VSS
RI1*
DSR1*
CLK
CSO)
VSS
LPTOE*
ACK
PE
BUSY
SLCT
VCC
ERROR*
STS1
RXRdy1
1
408-432-9100/www.impweb.com
VSS
DSRO*
RLSD0*
RI0*
DSR*
CSO*
A2
A1
AO
IOW*
IOR*
CSO*
RESET鈥?/div>
VCC
SIN0
TXRDy1*
VSS
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
SOUT1
DTR1*
RTS1*
DSR1*
D0
D1
D2
D3
D4
D5
D6
D7
TXRdy0*
VCC
RTS0*
DTR0*
SOUT0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
IMP
16C552
DSR*D
INT2
SLIN*+
INIT*+
AFD*+
STB*+
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INT0
BDO
漏 2002 IMP, Inc.

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