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IDTCV110JPV Datasheet

  • IDTCV110JPV

  • PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

  • 16頁

  • IDT

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IDTCV110J
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV110J
FEATURES:
DESCRIPTION:
鈥?One high precision PLL for CPU, SSC, and N programming
鈥?One high precision PLL for SRC/PCI/SATA, SSC, and N
programming
鈥?One high precision PLL for 96MHz/48MHz
鈥?Band-gap circuit for differential outputs
鈥?Support spread spectrum modulation, down spread 0.5%
鈥?Support SMBus block read/write, index read/write
鈥?Selectable output strength for REF
鈥?Allows for CPU frequency to change to a higher frequency for
maximum system computing power
鈥?Available in SSOP package
IDTCV110J is a 56 pin clock device. The CPU output buffer is designed to
support up to 400MHz processor. This chip has three PLLs inside for CPU/
SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced I
REF
to reduce the impact of V
DD
variation on differential
outputs, which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, worse case 114
ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock
has its own Spread Spectrum selection, which allows for isolated changes
instead of affecting other clock groups.
OUTPUTS:
鈥?2*0.7V current 鈥搈ode differential CPU CLK pair
鈥?6*0.7V current 鈥搈ode differential SRC CLK pair, one dedicated
for SATA
鈥?One CPU_ITP/SRC selectable CLK pair
鈥?9*PCI, 3 free running, 33.3MHz
鈥?1*96MHz, 1*48MHz
鈥?1*REF
KEY SPECIFICATION:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
CPU/SRC CLK cycle to cycle jitter < 85ps
SATA CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
N Programmable
CPU CLK
Output Buffers
Stop Logic
CPU[1:0]
X1
XTAL
Osc Amp
CPU_ITP/SRC7
I
REF
REF
ITP_EN
X2
SDATA
SCLK
SM Bus
Controller
PLL2
SSC
N Programmable
SRC CLK
Output Buffer
Stop Logic
SRC[6:1]
PCI[5:0], PCIF[2:0]
I
REF
V
TT_PWRGD
#/PD
Control
Logic
FSA.B.C
PLL3
48MHz/96MHz
Output BUffer
DOT96
48MHz
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
漏 2004 Integrated Device Technology, Inc.
MAY 2004
DSC-6507/12

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