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IDTCSPT857APA Datasheet

  • IDTCSPT857APA

  • 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

  • 12頁(yè)

  • IDT

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IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
FEATURES:
DESCRIPTION:
IDTCSPT857/A
鈥?Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
鈥?Operating frequency: 60MHz to 200MHz
鈥?Standard speed: PC1600 (DDR200), PC2100 (DDR266)
鈥?A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
鈥?1 to 10 differential clock distribution
鈥?Very low skew (<100ps)
鈥?Very low jitter (<75ps)
鈥?2.5V AV
DD
and 2.5V V
DDQ
鈥?CMOS control signal input
鈥?Test mode enables buffers while disabling PLL
鈥?Low current power-down mode
鈥?Tolerant of Spread Spectrum input clock
鈥?Available in 48-pin TSSOP and 56-pin VFBGA packages
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential output
pairs (Y
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output (FBOUT,
FBOUT).
External feedback pins (FBIN,
FBIN)
for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the output frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption device of less than 200碌A(chǔ).
The CSPT857 requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857 is only available in Industrial Temperature Range (-40擄C to
+85擄C), and CSPT857A is only available in Commercial Temperature Range
(0擄C to +70擄C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
PWRDWN
37/E6
AV
DD
16/G2
TEST
MODE
LOGIC
3/A1
Y0
2/A2
Y0
5/B2
6/B1
10/D1
9/D2
Y1
Y1
Y2
Y2
20/J2
Y3
19/J1
22/K1
Y3
Y4
23/K2
Y4
Y5
CLK
CLK
FBIN
FBIN
13/F1
14/F2
46/A6
47/A5
44/B5
43/B6
39/D6
40/D5
29/J5
30/J6
PLL
36/F6
35/F5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
27/K6
26/K5
32/H6
33/H5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2002
Integrated Device Technology, Inc.
OCTOBER 2002
DSC-5172/8

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