IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
FEATURES:
DESCRIPTION:
IDT5T940
鈥?Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
鈥?3-level inputs for feedback divide ratio and output frequency range
selection
鈥?1x, 2x, 4x, 8x, 16x, and 32x outputs on Q
OUT
鈥?Regenerated input clock or Q
OUT
/4 on Q
REG
鈥?Lock indicator
鈥?Power-down mode
鈥?LVPECL or LVDS outputs
鈥?Three modes of output frequency range
- Mode 0: Q
OUT
range 155.5 - 166.6MHz. Q
REG
is a regenerated version
of the input clock.
- Mode 1: Q
OUT
range 622 - 666.5MHz. Q
REG
output 155.5-166.6MHz.
- Mode 2: Q
OUT
range 622 - 666.5MHz. Q
REG
is a regenerated version
of the input clock frequency.
鈥?Selectable loop bandwidths
鈥?Hitless switchover
鈥?Differential LVPECL, LVDS, or single-ended LVTTL input interface
鈥?2.375 - 3.465V core and I/O
鈥?Available in VFQFPN package
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
The three modes of output frequency range are controlled by the SELmode,
which is a 3-level pin. When SELmode is high or low, the Q
OUT
is a multiplied
version of the input clock while Q
REG
is a regenerated version of the input clock.
When SELmode is mid, the Q
OUT
is a multiplied version of the input clock while
Q
REG
is Q
OUT
/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Terabit routers
Gigabit ethernet systems
SONET / SDH systems
Digital cross connects
Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
PLLBW
1
PLLBW
0
Q
REG
PLL
DIV
N
Q
REG
CLKIN
CLKIN
INPUT
MUX
Q
OUT
DIV
M
Q
OUT
REFIN
REFIN
LOCK,
FREQ.
DETECTOR
CONTROL
LOGIC
PD
LOCK
SEL
MODE
CLK/
REF
0
CLK/
REF
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2003
Integrated Device Technology, Inc.
DECEMBER 2003
DSC 6195/23
IDT5T940-10NLI相關(guān)型號PDF文件下載
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