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IDT5T93GL04PGI Datasheet

  • IDT5T93GL04PGI

  • 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFERII

  • 17頁

  • IDT

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2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER
TERABUFFER鈩?II
General
Description
The IDT5T93GL04 2.5V differential clock buffer is a
user-selectable differential input to four LVDS outputs. The fanout
from a differential input to four LVDS outputs reduces loading on
the preceding driver and provides an efficient clock distribution
network. The IDT5T93GL04 can act as a translator from a
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V
LVTTL input can also be used to translate to LVDS outputs. The
redundant input capability allows for
a
glitchless change-over from
a primary clock source to a secondary clock source up to 450MHz.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable low for up to three clock cycles of the
previously-selected input clock. The outputs will remain low for up
to three clock cycles of the newly-selected clock, after which the
outputs will start from the newly-selected input. A FSEL pin has
been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T9304 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the
GL pin. Multiple power and grounds reduce noise.
IDT5T93GL04
Features
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Guaranteed low skew: <50ps (maximum)
Very low duty cycle distortion: <100ps (maximum
High speed propagation delay: <2.2ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to four LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
DD
-40擄C to 85擄C ambient operating temperature
Available in TSSOP package
Applications
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Clock distribution
Pin Assignment
GND
PD
FSEL
V
DD
Q1
Q1
Q2
Q2
V
DD
SEL
G
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A2
A2
GND
V
DD
Q3
Q3
Q4
Q4
V
DD
GL
A1
A1
24-Lead TSSOP
4.4mm x 7.8mm x 1.0mm package body
G Package
Top View
IDT鈩?LVDS GLITCHLESS CLOCK BUFFER TERABUFFER鈩?II
1
IDT5T93GL04 REV. A JULY 10, 2007

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