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IDT5T9310NLI Datasheet

  • IDT5T9310NLI

  • 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II

  • 91.69KB

  • 12頁

  • IDT

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IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
2.5V LVDS 1:10
CLOCK BUFFER
TERABUFFER鈩?II
FEATURES:
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IDT5T9310
DESCRIPTION:
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion < 125ps (max)
High speed propagation delay < 1.75ns (max)
Up to 1GHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
Selectable differential inputs to ten LVDS outputs
Power-down mode
2.5V V
DD
Available in VFQFPN package
The IDT5T9310 2.5V differential clock buffer is a user-selectable differential
input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs
reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9310 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
The IDT5T9310 outputs can be asynchronously enabled/disabled. When
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
APPLICATIONS:
鈥?Clock distribution
FUNCTIONAL BLOCK DIAGRAM
GL
G1
OUTPUT
CONTROL
Q1
Q1
PD
OUTPUT
CONTROL
Q2
Q2
A1
A1
1
OUTPUT
CONTROL
Q3
Q3
A2
A2
0
OUTPUT
CONTROL
Q4
Q4
SEL
OUTPUT
CONTROL
Q5
Q5
G2
OUTPUT
CONTROL
Q6
Q6
OUTPUT
CONTROL
Q7
Q7
OUTPUT
CONTROL
Q8
Q8
OUTPUT
CONTROL
Q9
Q9
OUTPUT
CONTROL
Q10
Q10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
MARCH 2004
DSC-6175/13
漏 2004 Integrated Device Technology, Inc.

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