鈥?/div>
IDT5T907
DESCRIPTION:
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion
High speed propagation delay < 2.5ns. (max)
Up to 250MHz operation
Very low CMOS power levels
1.5V V
DDQ
for HSTL interface
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
鈥?Selectable differential or single-ended inputs and ten single-
ended outputs
鈥?2.5V V
DD
鈥?Available in TSSOP package
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to ten single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a single
or differential input to ten single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels.
The IDT5T907 has two output banks that can be asynchronously enabled/
disabled. Multiple power and grounds reduce noise.
鈥?Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
TxS
GL
G1
O UTPUT
CO NTR OL
Q
1
O UTPUT
CO NTR OL
Q
2
O UTPUT
CO NTR OL
Q
3
RxS
A
A/V
R EF
O UTPUT
CO NTR OL
Q
4
O UTPUT
CO NTR OL
Q
5
G2
O UTPUT
CO NTR OL
Q
6
O UTPUT
CO NTR OL
Q
7
O UTPUT
CO NTR OL
Q
8
O UTPUT
CO NTR OL
Q
9
O UTPUT
CO NTR OL
Q
10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
FEBRUARY 2003
DSC-5899/22
漏 2003 Integrated Device Technology, Inc.