鈥?/div>
IDT5T9070
DESCRIPTION:
Optimized for 2.5V LVTTL
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion < 300ps (max)
High speed propagation delay < 2ns. (max)
Up to 200MHz operation
Very low CMOS power levels
Hot insertable and over-voltage tolerant inputs
1:10 fanout buffer
2.5V V
DD
Available in TSSOP package
The IDT5T9070 2.5V single data rate (SDR) clock buffer is a single-ended
input to ten single-ended outputs buffer built on advanced metal CMOS
technology. The SDR clock buffer fanout from a single input to ten single-ended
outputs reduces the loading on the preceding driver and provides an efficient
clock distribution network.
The IDT5T9070 has two output banks that can be asynchronously enabled/
disabled. Multiple power and grounds reduce noise.
鈥?Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
GL
G1
OU TPUT
CON TROL
Q
1
OU TPUT
CON TROL
Q
2
OU TPUT
CON TROL
Q
3
A
OU TPUT
CON TROL
Q
4
OU TPUT
CON TROL
Q
5
G2
OU TPUT
CON TROL
Q
6
OU TPUT
CON TROL
Q
7
OU TPUT
CON TROL
Q
8
OU TPUT
CON TROL
Q
9
OU TPUT
CON TROL
Q
10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
OCTOBER 2002
DSC-5960/18
漏 2002 Integrated Device Technology, Inc.