鈥?/div>
IDT5T9050
DESCRIPTION:
Optimized for 2.5V LVTTL
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion < 300 (max)
High speed propagation delay < 1.8ns. (max)
Up to 200MHz operation
Very low CMOS power levels
Hot insertable and over-voltage tolerant inputs
1:5 fanout buffer
2.5V V
DD
Available in TSSOP package
The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended
input to five single-ended outputs buffer built on advanced metal CMOS
technology. The SDR clock buffer fanout from a single input to five single-ended
outputs reduces the loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise.
鈥?Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
GL
G
O U TPUT
C O N TR O L
Q
1
O U TPUT
C O N TR O L
Q
2
A
O U TPUT
C O N TR O L
Q
3
O U TPUT
C O N TR O L
Q
4
O U TPUT
C O N TR O L
Q
5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
OCTOBER 2002
DSC-5958/17
漏 2002 Integrated Device Technology, Inc.