TURBOCLOCK鈩?/div>
FEATURES:
DESCRIPTION:
IDT5993A
鈥?3 pairs of programmable skew outputs
鈥?Low skew: 200ps same pair, 250ps all outputs
鈥?Selectable positive or negative edge synchronization:
Excellent for DSP applications
鈥?Synchronous output enable
鈥?Output frequency: 3.75MHz to 100MHz
鈥?2x, 4x, 1/2, and 1/4 outputs
鈥?5V with TTL outputs
鈥?3 skew grades:
IDT5993A-2: t
SKEW0
<250ps
IDT5993A-5: t
SKEW0
<500ps
IDT5993A-7: t
SKEW0
<750ps
鈥?3-level inputs for skew and PLL range control
鈥?PLL bypass for DC testing
鈥?External feedback, internal loop filter
鈥?46mA I
OL
high drive outputs
鈥?Low Jitter: <200ps peak-to-peak
鈥?Outputs drive 50鈩?terminated lines
鈩?/div>
鈥?Available in QSOP package
The IDT5993A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5993A has six programmable skew
outputs and two zero skew outputs. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
FUNCTIONAL BLOCK DIAGRAM
G ND/sO E
Skew
Select
3
3
1F1:0
V
CCQ
/PE
Skew
Select
REF
PLL
FB
3
FS
Skew
Select
3
3
3F1:0
3
3
2F1:0
1Q
0
1Q
1
2Q
0
2Q
1
3Q
0
3Q
1
4Q
0
4Q
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2001
Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC 5844/1
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