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IDT54FCT821ATSOB Datasheet

  • IDT54FCT821ATSOB

  • HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

  • 182.52KB

  • 9頁

  • IDT

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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS
Integrated Device Technology, Inc.
IDT54/74FCT821AT/BT/CT
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
FEATURES:
鈥?Common features:
鈥?Low input and output leakage
鈮?碌A(chǔ)
(max.)
鈥?CMOS power levels
鈥?True TTL input and output compatibility
鈥?V
OH
= 3.3V (typ.)
鈥?V
OL
= 0.3V (typ.)
鈥?Meets or exceeds JEDEC standard 18 specifications
鈥?Product available in Radiation Tolerant and Radiation
Enhanced versions
鈥?Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
鈥?Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
鈥?Features for FCT821T/FCT823T/FCT825T:
鈥?A, B, C and D speed grades
鈥?High drive outputs (-15mA I
OH
, 48mA I
OL
)
鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis-
ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (
EN
) and Clear (
CLR
) 鈥?ideal for parity bus
interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (
OE
1,
OE
2,
OE
3) to allow multi-
user control of the interface, e.g.,
CS
, DMA and RD/
WR
. They
are ideal for use as an output port requiring high I
OL
/I
OH
.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
EN
D
N
CLR
D
CL
Q
D
CL
Q
CP Q
CP Q
CP
OE
Y
0
Y
N
2567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc
AUGUST 1995
DSC-4202/5
6.21
6.21
1
1

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