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IDT54FCT388915T133PYB Datasheet

  • IDT54FCT388915T133PYB

  • 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

  • 11頁

  • IDT

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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Integrated Device Technology, Inc.
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
IDT54/74FCT388915T
70/100/133/150
PRELIMINARY
is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of
鈥?0.5 MICRON CMOS Technology
the phase/frequency detector, charge pump, loop filter and
鈥?Input frequency range: 10MHz 鈥?f2Q Max. spec
VCO. The VCO is designed for a 2Q operating frequency
(FREQ_SEL = HIGH)
range of 40MHz to f2Q Max.
鈥?Max. output frequency: 150MHz
The IDT54/74FCT388915T provides 8 outputs with 350ps
鈥?Pin and function compatible with FCT88915T, MC88915T
skew. The
Q5
output is inverted from the Q outputs. The 2Q
鈥?5 non-inverting outputs, one inverting output, one 2x
runs at twice the Q frequency and Q/2 runs at half the Q
output, one
梅2
output; all outputs are TTL-compatible
frequency.
鈥?3-State outputs
The FREQ_SEL control provides an additional
梅
2 option in
鈥?Output skew < 350ps (max.)
the output path. PLL _EN allows bypassing of the PLL, which
鈥?Duty cycle distortion < 500ps (max.)
is useful in static test modes. When PLL_EN is low, SYNC
鈥?Part-to-part skew: 1ns (from t
PD
max. spec)
input may be used as a test clock. In this test mode, the input
鈥?32/鈥?6mA drive at CMOS output voltage levels
frequency is not limited to the specified range and the polarity
鈥?V
CC
= 3.3V
鹵
0.3V
of outputs is complementary to that in normal operation
鈥?Inputs can be driven by 3.3V or 5V components
(PLL_EN = 1). The LOCK output attains logic HIGH when the
鈥?Available in 28 pin PLCC, LCC and SSOP packages
PLL is in steady-state phase and frequency lock. When OE/
DESCRIPTION:
RST
is low, all the outputs are put in high impedance state and
The IDT54/74FCT388915T uses phase-lock loop technol- registers at Q,
Q
and Q/2 outputs are reset.
ogy to lock the frequency and phase of outputs to the input
The IDT54/74FCT388915T requires one external loop filter
reference clock. It provides low skew clock distribution for component as recommended in Figure 3.
high performance PCs and workstations. One of the outputs
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
Phase/Freq.
Detector
Voltage
Controlled
Oscilator
LF
REF_SEL
PLL_EN
0
1
Mux
2Q
(
梅
1)
(
梅
2)
1M
u
x
0
D
Q
LOCK
0M
u
1x
Charge Pump
SYNC (0)
SYNC (1)
Q0
Q1
Divide
-By-2
FREQ_SEL
OE/RST
CP
R
Q
D
CP
R
D
CP
R
D
CP
D
CP
D
CP
D
CP
R
3052 drw 01
R
R
R
Q
Q
Q2
Q
Q3
Q
Q4
Q5
Q
Q
Q/2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-4243/1
9.8
9.8
1
1

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