3.3V CMOS OCTAL
TRANSPARENT
LATCHES
Integrated Device Technology, Inc.
IDT54/74FCT3573/A
ADVANCE INFORMATION
FEATURES:
鈥?0.5 MICRON CMOS Technology
鈥?ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
鈥?25 mil Center SSOP Packages
鈥?Extended commercial range of -40擄C to +85擄C
鈥?V
CC
= 3.3V
鹵0.3V,
Normal Range or
V
CC
= 2.7V to 3.6V, Extended Range
鈥?CMOS power levels (0.4碌W typ. static)
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The FCT3573/A are octal transparent latches built using an
advanced dual metal CMOS technology.
These octal latches have 3-state outputs and are intended
for bus oriented applications. The flip-flops appear transpar-
ent to the data when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the set-up time is latched. Data
appears on the bus when the Output Enable (
OE
) is LOW.
When
OE
is HIGH, the bus output is in the high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
D
0
D
O
G
G
D
1
D
O
G
D
2
D
O
G
D
3
D
O
G
D
4
D
O
G
D
5
D
O
G
D
6
D
O
G
D
7
D
O
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
3093 drw 01
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
2
3
4
5
6
7
8
9
10
20
19
P20-1
D20-1 17
SO20-2 16
&
15
SO20-7
14
13
12
11
18
V
CC
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
3093 drw 02
FUNCTION TABLE
(1)
D
N
H
L
X
Inputs
LE
H
H
X
OE
L
L
H
Outputs
O
N
H
L
Z
3093 tbl 02
NOTE:
1. H = HIGH Voltage Level
X = Don鈥檛 Care
L = LOW Voltage Level
Z = High Impedance
DEFINITION OF FUNCTIONAL TERMS
Pin Names
D
N
LE
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
Complementary 3-State Outputs
3093 tbl 03
DIP/SOIC/SSOP
TOP VIEW
OE
O
N
O
N
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-4648/-
8.13
1
1
2
3
4
5
6
7
