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IDT54FCT273ASOB Datasheet

  • IDT54FCT273ASOB

  • FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET

  • 64.80KB

  • 7頁(yè)

  • IDT

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廬
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
DESCRIPTION:
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
Integrated Device Technology, Inc.
FEATURES:
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IDT54/74FCT273 equivalent to FAST鈩?speed;
IDT54/74FCT273A 45% faster than FAST
IDT54/74FCT273C 55% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
I
OL
= 48mA (commercial) and 32mA (military)
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5碌A(chǔ) max.)
Octal D flip-flop with Master Reset
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset ( ) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop鈥檚 O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
MR
MR
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
D
CP
R
D
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2558 drw 01
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
D
CP
Q
R
D
PIN CONFIGURATIONS
D
0
O
0
MR
Vcc
O
7
3 2
4
5
6
7
8
O
3
GND
CP
O
4
D
4
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
P20-1
D20-1
SO20-2
&
E20-1
17
16
15
14
13
12
11
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
INDEX
D
1
O
1
O
2
D
2
D
3
L20-2
20 19
18
1
17
16
15
14
9 10 11 12 13
D
7
D
6
O
6
O
5
D
5
2558 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4609/2
7.10
1

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