鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25擄C
鈥?Features for FCT162823AT/BT/CT/ET:
鈥?Balanced Output Drivers:
鹵24mA
(commercial),
鹵16mA
(military)
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25擄C
DESCRIPTION:
The FCT16823AT/BT/CT/ET and FCT162823AT/BT/CT/
ET 18-bit bus interface registers are built using advanced,
dual metal CMOS technology. These high-speed, low-power
registers with clock enable (x
CLKEN
) and clear (x
CLR
) con-
trols are ideal for parity bus interfacing in high-performance
synchronous systems. The control inputs are organized to
operate the device as two 9-bit registers or one 18-bit register.
Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise mar-
gin.
The FCT16823AT/BT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162823AT/BT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times 鈥?reduc-
ing the need for external series terminating resistors. The
FCT162823AT/BT/CT/ET are plug-in replacements for the
FCT16823AT/BT/CT/ET and ABT16823 for on-board inter-
face applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
CLR
1
CLK
1
CLKEN
2
OE
2
CLR
2
CLK
2
CLKEN
R
C
D
1
D
1
1
Q
1
2
D
1
R
C
D
2
Q
1
TO 8 OTHER CHANNELS
2772 drw 01
TO 8 OTHER CHANNELS
2772 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2772/8
5.16
1