Integrated Device Technology, Inc.
CMOS technology. These high-speed, low-power 18-bit reg-
latched or clocked mode. Each direction has an independent
鈥?/div>
Typical t
SK
(o) (Output Skew) < 250ps
independent output enable. The package is organized with a
鈥?Low input and output leakage
鈮?碌A(chǔ)
(max.)
flow-through signal pin organization to ease board layout. All
鈥?ESD > 2000V per MIL-STD-883, Method 3015;
inputs are designed with hysteresis for improved noise mar-
> 200V using machine model (C = 200pF, R = 0)
gin.
鈥?Packages include 25 mil pitch SSOP, 19.6 mil pitch
This transceiver is ideally suited for high speed memory
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
interfaces which utilize high speed synchronous writes, by
鈥?Extended commercial range of -40擄C to +85擄C
clocking the data into a high speed register. Reads can then
鈥?V
CC
= 5V
鹵10%
be performed in a transparent or latched mode utilizing the
鈥?Features for FCT16601AT/CT/ET:
same transceiver.
鈥?High drive outputs (-32mA I
OH
, 64mA I
OL
)
The FCT16601AT/CT/ET are ideally suited for driving
鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
high-capacitance loads and low-impedance backplanes. The
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V at
output buffers are designed with power off disable capability
V
CC
= 5V, T
A
= 25擄C
to allow "live insertion" of boards when used as backplane
鈥?Features for FCT162601AT/CT/ET:
drivers.
鈥?Balanced Output Drivers:
鹵24mA
The FCT162601AT/CT/ET have balanced output drive
鈥?Reduced system switching noise
with current limiting resistors. This offers low ground bounce,
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V at
minimal undershoot, and controlled output fall times鈥搑educing
V
CC
= 5V,T
A
= 25擄C
the need for external series terminating resistors. The
FCT162601AT/CT/ET are plug-in replacements for the
DESCRIPTION:
FCT16601AT/CT/ET and ABT16601 for on-board bus inter-
The FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications.
FEATURES:
P
R
E
V
E
I
W
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
1
56
55
2
28
30
P
29
27
3
R
O
D
C
U
T
A
1
CE
1D
C1
CLK
CE
1D
C1
CLK
54
B
1
3247 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
COMMERCIAL TEMPERATURE RANGE
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
5.9
DSC-3247/-
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