鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25擄C
鈥?Features for FCT162374T/AT/CT/ET:
鈥?Balanced Output Drivers:
鹵24mA
(commercial),
鹵16mA
(military)
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25擄C
DESCRIPTION:
The FCT16374T/AT/CT/ET and FCT162374T/AT/CT/ET
16-bit edge-triggered D-type registers are built using ad-
vanced dual metal CMOS technology. These high-speed,
low-power registers are ideal for use as buffer registers for
data synchronization and storage. The Output Enable (x
OE
)
and clock (xCLK) controls are organized to operate each
device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins sim-
plifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16374T/AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162374T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times鈥?reduc-
ing the need for external series terminating resistors. The
FCT162374T/AT/CT/ET are plug-in replacements for the
FCT16374T/AT/CT/ET and ABT16374 for on-board bus inter-
face applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
CLK
1
D
1
2
OE
2
CLK
D
1
O
1
2
D
1
D
2
O
1
C
C
TO 7 OTHER CHANNELS
2542 drw 01
TO 7 OTHER CHANNELS
2542 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FEBRUARY 1997
DSC-2542/9
漏1997
Integrated Device Technology, Inc.
5.8
For the latest information regarding this part, please contact IDT's web site at http://www.idt.com or fax-on-demand service at (US)1-800-9-IDT-FAX / (International) 408-492-8391.
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