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IDT54FCT163652A Datasheet

  • IDT54FCT163652A

  • 3.3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS

  • 9頁(yè)

  • IDT

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廬
Integrated Device Technology, Inc.
3.3V CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS
IDT54/74FCT163652/A/C
PRODUCT PREVIEW
FEATURES:
鈥?0.5 MICRON CMOS Technology
鈥?/div>
Typical t
SK
(o) (Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
鈥?Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
鈥?Extended commercial range of -40擄C to +85擄C
鈥?V
CC
= 3.3V
鹵0.3V,
Normal Range or
V
CC
= 2.7 to 3.6V, Extended Range
鈥?CMOS power levels (0.4碌W typ. static)
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Military product compliant to MIL-STD-883, Class B
鈥?Low Ground Bounce (0.3V typ.)
鈥?Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The IDT54/74FCT163652/A/C 16-bit registered transceiv-
ers are built using advanced dual metal CMOS technology.
These high-speed, low-power devices are organized as two
independent 8-bit bus transceivers with 3-state D-type regis-
ters. For example, the xOEAB and x
OEBA
signals control the
transceiver functions.
The xSAB and xSBA control pins are provided to select
either real time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that
occurs in a multiplexer during the transition between stored
and real time data. A LOW input level selects real-time data
and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The IDT54/74FCT163652/A/C have series current limiting
resistors. This offers low ground bounce, minimal under-
shoot, and controlled output fall times鈥搑educing the need for
external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
1
OEAB
1
OEBA
1
CLKBA
1
SBA
1
CLKAB
1
SAB
B REG
2
OEAB
2
OEBA
2
CLKBA
2
SBA
2
CLKAB
2
SAB
B REG
D
C
1
A
1
A REG
1
B
1
2
A
1
A REG
D
C
2
B
1
D
C
D
C
TO 7 OTHER CHANNELS
3084 drw 01
TO 7 OTHER CHANNELS
3084 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-3084/2
8.7
1

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