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IDT54FCT16270ATPAB Datasheet

  • IDT54FCT16270ATPAB

  • FAST CMOS 18-BIT R/W BUFFER

  • 9頁

  • IDT

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FAST CMOS 18-BIT
R/W BUFFER
Integrated Device Technology, Inc.
IDT54/74FCT162701T/AT
FEATURES:
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0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
鈮?碌A(chǔ)
(max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40擄C to +85擄C
Balanced Output Drivers:
鹵24mA
(commercial),
鹵16mA
(military)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V, T
A
= 25擄C
Ideal for new generation x86 write-back cache solutions
Suitable for modular x86 architectures
Four deep write FIFO
Latch in read path
Synchronous FIFO reset
DESCRIPTION:
The FCT162701T/AT is an 18-bit Read/Write buffer with
a four deep FIFO and a read-back latch. It can be used as
a read/write buffer between a CPU and memory or to
interface a high-speed bus and a slow peripheral. The A-
to-B (write) path has a four deep FIFO for pipelined opera-
tions. The FIFO can be reset and a FIFO full condition is
indicated by the full flag (
FF
). The B-to-A (read) path has a
latch. A HIGH on LE, allows data to flow transparently from
B-to-A. A LOW on LE allows the data to be latched on the
falling edge of LE.
The FCT162701T/AT has a balanced output drive with
series termination. This provides low ground bounce,
minimal undershoot and controlled output edge rates.
FUNCTIONAL BLOCK DIAGRAM
A
1-18
18
OEBA
RESET
CLK
WCE
RCE
FF
FIFO
(4 deep)
LATCH
LE
OEAB
18
2915 drw 01
B
1-18
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2915/3
5.15
1

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