鈥?/div>
The IDT54/74FCT139T/AT/CT are dual 1-of-4 decoders
built using an advanced dual metal CMOS technology. These
devices have two independent decoders, each of which
accept two binary weighted inputs (A
0
-A
1
) and provide four
mutually exclusive active LOW outputs (
O
0
-
O
3
). Each de-
coder has an active LOW enable (
E
). When
E
is HIGH, all
outputs are forced HIGH.
FUNCTIONAL BLOCK DIAGRAM
E
a
A
0a
A
1a
E
b
A
0b
A
1b
PIN CONFIGURATIONS
E
a
A
0a
A
1a
O
0a
O
1a
O
2a
O
3a
GND
1
2
3
4
5
6
7
8
P16-1
D16-1
SO16-1
SO16-7
&
E16-1
16
15
14
13
12
11
10
9
V
CC
E
b
A
0b
A
1b
O
0b
O
1b
O
2b
O
3b
2566 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
E
a
V
CC
A
0a
NC
1
INDEX
O
0a
O
1a
O
2a
O
3a
O
0b
O
1b
O
2b
O
3b
2566 drw 01
3 2
A
1a
O
0a
NC
O
1a
O
2a
4
5
6
7
8
20 19
18
17
16
15
14
E
b
A
0b
A
1b
NC
O
0b
O
1b
L20-2
9 10 11 12 13
GND
NC
O
3b
O
3a
O
2b
2566 drw 03
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4218/3
6.4
1