鈥?/div>
The IDT54/74FCT138T/AT/CT are 1-of-8 decoders built
using an advanced dual metal CMOS technology. The IDT54/
74FCT138T/AT/CT accepts three binary weighted inputs (A
0
,
A
1
, A
2
) and, when enabled, provides eight mutually exclusive
active LOW outputs (
O
0
-
O
7
). The IDT54/74FCT138T/AT/CT
features three enable inputs, two active LOW (
E
1
,
E
2
) and one
active HIGH (E
3
). All outputs will be HIGH unless
E
1
and
E
2
are
LOW and E
3
is HIGH. This multiple enable function allows
easy parallel expansion of the device to a 1-of-32 (5 lines to
32 lines) decoder with just four IDT54/74FCT138T/AT/CT
devices and one inverter.
FUNCTIONAL BLOCK DIAGRAM
A
2
A
1
A
0
E
1
E
2
E
3
PIN CONFIGURATIONS
A
0
A
1
A
2
E
1
E
2
E
3
O
7
GND
1
2
3
4
5
6
7
8
P16-1
D16-1
SO16-1
SO16-7
&
E16-1
16
15
14
13
12
11
10
9
V
CC
O
0
O
1
O
2
O
3
O
4
O
5
O
6
2570 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
INDEX
V
CC
NC
1
A
1
A
0
3 2
A
2
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
2570 drw 01
4
5
6
7
8
20 19
18
17
16
15
14
O
0
O
1
O
2
NC
O
3
O
4
E
1
NC
E
2
E
3
L20-2
9 10 11 12 13
GND
NC
O
7
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc.
O
6
O
5
2570 drw 03
APRIL 1995
DSC-4213/5
6.3
1