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0.5 MICRON CMOS Technology
Guaranteed low skew < 500ps (max.)
Very low duty cycle distortion < 1.0ns (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
V
CC
= 3.3V 鹵 0.3V
Available in SSOP, SOIC, and QSOP packages
DESCRIPTION:
The FCT3805 is a 3.3 volt, non-inverting clock driver built using
advanced dual metal CMOS technology. The device consists of two banks
of drivers, each with a 1:5 fanout and its own output enable control. The
device has a "heartbeat" monitor for diagnostics and PLL driving. The
MON output is identical to all other outputs and complies with the output
specifications in this document. The FCT3805 offers low capacitance inputs
with hysteresis.
The FCT3805 is designed for high speed clock distribution where signal
quality and skew are critical. The FCT3805 also allows single point-to-
point transmission line driving in applications such as address distribution,
where one signal must be distributed to multiple recievers with low skew
and high signal quality.
FUNCTIONAL BLOCK DIAGRAM
OE
A
5
IN
A
OA
1
- OA
5
PIN CONFIGURATION
V
CC A
OA
1
OA
2
OA
3
GND
A
1
2
3
4
5
6
7
8
9
10
SO20-2
SO20-7
SO20-8
20
19
18
17
16
15
14
13
12
11
V
CC B
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
M ON
OE
B
IN
B
IN
B
OE
B
5
OA
4
OB
1
- OB
5
OA
5
GND
Q
M ON
OE
A
IN
A
SOIC/ SSOP/ QSOP
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
c
2001
Integrated Device Technology, Inc.
JULY 2001
DSC-3102