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IDT49C460EGB Datasheet

  • IDT49C460EGB

  • 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

  • 32頁

  • IDT

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32-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT
Integrated Device Technology, Inc.
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
IDT49C460E
FEATURES:
鈥?Fast
鈥?IDT49C460E
鈥?IDT49C460D
鈥?IDT49C460C
鈥?IDT49C460B
鈥?IDT49C460A
鈥?IDT49C460
Low-power CMOS
鈥?Commercial: 95mA (max.)
鈥?Military: 125mA (max.)
Improves system memory reliability
鈥?Corrects all single bit errors, detects all double and some
triple-bit errors
Cascadable
鈥?Data words up to 64-bits
Built-in diagnostics
鈥?Capable of verifying proper EDC operation via software
control
Simplified byte operations
鈥?Fast byte writes possible with separate byte enables
Functional replacement for 32- and 64-bit configurations of
the AM29C60 and AM29C660
Available in PGA, PLCC and Fine Pitch Flatpack
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962鈥?8533
Detect
10ns (max.)
12ns (max.)
16ns (max.)
25ns (max.)
30ns (max.)
40ns (max.)
Correct
14ns (max.)
18ns (max.)
24ns (max.)
30ns (max.)
36ns (max.)
49ns (max.)
DESCRIPTION:
The IDT49C460s are high-speed, low-power, 32-bit Error
Detection and Correction Units which generate check bits on
a 32-bit data field according to a modified Hamming Code and
correct the data word when check bits are supplied. The
IDT49C460s are performance-enhanced functional replace-
ments for 32-bit versions of the 2960. When performing a read
operation from memory, the IDT49C460s will correct 100% of
all single bit errors and will detect all double bit errors and
some triple bit errors.
The IDT49C460s are easily cascadable to 64-bits. Thirty-
two-bit systems use 7 check bits and 64-bit systems use 8
check bits. For both configurations, the error syndrome is
made available.
The IDT49C460s incorporate two built-in diagnostic modes.
Both simplify testing by allowing for diagnostic data to be
entered into the device and to execute system diagnostics
functions.
They are fabricated using a CMOS technology designed for
high-performance and high-reliability. The devices are pack-
aged in a 68-pin ceramic PGA, PLCC and Ceramic Quad
Flatpack.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FUNCTIONAL BLOCK DIAGRAM
CB
0鈥?
DATA
0鈥?1
8
DATA
LATCH
4
8
32
32
DATA
LATCH
CHECK BIT
GENERATE
8
MUX
MUX
CHECK BIT
IN LATCH
LE
IN
13
MUX
DIAGNOSTIC
LATCH
8
5
CONTROL
LOGIC
8
SC
0鈥?
32
ERROR
CORRECT
ERROR
DECODE
8
MUX
OE
BYTE
0鈥?
OE
SC
SYNDROME
GENERATE
ERROR
DETECT
ERROR
MULT ERROR
LE
DIAG
LE
OUT
/
GENERATE
CORRECT
CODE ID
1,0
DIAG MODE
1,0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2584 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-9017/8
11.6
1

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