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IDT2308-1HPGI Datasheet

  • IDT2308-1HPGI

  • 3.3V ZERO DELAY CLOCK MULTIPLIER

  • 13頁

  • IDT

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IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK MULTIPLIER
FEATURES:
DESCRIPTION:
IDT2308
鈥?Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
鈥?Distributes one clock input to two banks of four outputs
鈥?Separate output enable for each output bank
鈥?External feedback (FBK) pin is used to synchronize the outputs
to the clock input
鈥?Output Skew <200 ps
鈥?Low jitter <200 ps cycle-to-cycle
鈥?1x, 2x, 4x output options (see table):
鈥?IDT2308-1 1x
鈥?IDT2308-2 1x, 2x
鈥?IDT2308-3 2x, 4x
鈥?IDT2308-4 2x
鈥?IDT2308-1H, -2H, and -5H for High Drive
鈥?No external RC network required
鈥?Operates at 3.3V V
DD
鈥?Available in SOIC and TSSOP packages
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308 enters power down, and the outputs are tri-stated. In
this mode, the device will draw less than 25碌A(chǔ).
The IDT2308 is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308 is characterized for both Industrial and Commercial operation.
NOTE:
For new designs, refer to AN-233.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
FBK
REF
16
1
2
(-5)
2
PLL
3
2
CLKA1
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
(-2, -3)
2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2003
Integrated Device Technology, Inc.
APRIL 2003
DSC 5173/9

IDT2308-1HPGI 產(chǎn)品屬性

  • Product Discontinuation 13/May/2009

  • 96

  • 集成電路 (IC)

  • 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器

  • -

  • 倍增器，零延遲緩沖器

  • 帶旁路

  • LVTTL

  • LVTTL

  • 1

  • 1:8

  • 無/無

  • 133.3MHz

  • 無/無

  • 3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-TSSOP（0.173"，4.40mm 寬）

  • 16-TSSOP

  • 管件

  • 2308-1HPGI

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