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ICSSSTV16857YL-T Datasheet

  • ICSSSTV16857YL-T

  • DDR 14-Bit Registered Buffer

  • 8頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICSSSTV16857
DDR 14-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
鈥?/div>
Differential clock signal
鈥?/div>
Meets SSTL_2 signal data
鈥?/div>
Supports SSTL_2 class I & II specifications
鈥?/div>
low-voltage operation
VDD = 2.3V to 2.7V
鈥?/div>
48 pin TSSOP package
Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
Truth Table
1
Inputs
RESET#
L
H
H
H
CLK
X or
Floating
鈫?/div>
鈫?/div>
L or H
CLK#
X or
Floating
鈫?/div>
鈫?/div>
L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q
0(2)
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1.
H = High Signal Level
L = Low Signal Level
鈫?/div>
= Transition LOW-to-HIGH
鈫?/div>
= Transition HIGH -to LOW
X = Irrelevant
Output level before the indicated
steady state input conditions were
established.
2.
Block Diagram
38
39
34
48
35
R
CLK
D1
CLK
CLK#
RESET#
D1
VREF
ICSSSTV16857
1
Q1
To 13 Other Channels
16857 Rev D 07/09/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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