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ICS9DB306 Datasheet

  • ICS9DB306

  • PCI Express, Jitter Attenuator

  • 273.90KB

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI E
XPRESS
,
J
ITTER
A
TTENUATOR
Features
鈥?/div>
Six differential LVPECL output pairs
鈥?/div>
1 differential clock input
鈥?/div>
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
鈥?/div>
Maximum output frequency: 140MHz
鈥?/div>
Output skew: 135ps (maximum)
鈥?/div>
Cycle-to-Cycle jitter: 25ps (maximum)
鈥?/div>
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
3ps (typical)
鈥?/div>
3.3V operating supply
鈥?/div>
0擄C to 70擄C ambient operating temperature
鈥?/div>
Lead-Free package fully RoHS compliant
鈥?/div>
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS9DB306 is a high performance 1-to-6
ICS
Differential-to LVPECL Jitter Attenuator designed
HiPerClockS鈩?/div>
for use in PCI Express鈩?systems. In some PCI
Express鈩?systems, such as those found in desktop
PCs, the PCI Express鈩?clocks are generated from
a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a zero delay buffer may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS9DB306 has 2 PLL bandwidth modes. In low
bandwidth mode, the PLL loop BW is about 500kHz and this
setting will attenuate much of the jitter from the reference clock
input while being high enough to pass a triangular input spread
spectrum profile. There is also a high bandwidth mode which
sets the PLL bandwidth at 1MHz which will pass more spread
spectrum modulation.
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express鈩?outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropri-
ate frequency select pins (FS0:1). Output PCIEX0 will always
run at the reference clock frequency (usually 100MHz) in desk-
top PC PCI Express鈩?Applications.
B
LOCK
D
IAGRAM
nOE0
1 Disabled
0 Enabled
梅5
Buffer
0
1
P
IN
A
SSIGNMENT
PCIEXT0
nPCIEXC0
V
EE
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
V
CC
nOE0
nOE1
V
CC
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
PCIEXC0
PCIEXT0
FS0
nCLK
CLK
PLL_BW
V
CCA
V
EE
BYPASS
FS1
PCIEXT5
PCIEXC5
V
CC
CLK
nCLK
Phase
Detector
Loop
Filter
VCO
0 梅4
1 梅5
0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
1
FS0
梅5
Internal Feedback
0 梅5
1 梅4
0
ICS9DB306
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
1
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm
body package
L Package
Top View
PCIEXT5
nPCIEXC5
ICS9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
F Package
Top View
FS1
BYPASS
nOE1
1 Disabled
0 Enabled
9DB306BL
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 7, 2005

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