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ICS954119YFLF-T Datasheet

  • ICS954119YFLF-T

  • Programmable Timing Control Hub⑩ for Next Gen P4⑩ processo...

  • 17頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
Programmable Timing Control Hub鈩?for Next Gen P4鈩?processor
Recommended Application:
CK410 compliant clock
Output Features:
鈥?/div>
2 - 0.7V current-mode differential CPU pairs
鈥?/div>
1 - 0.7V current-mode differential SRC pair
鈥?/div>
6 - PCI (33MHz)
鈥?/div>
3 - PCICLK_F, (33MHz) free-running
鈥?/div>
1 - USB, 48MHz
鈥?/div>
1 - 24/48 MHz
鈥?/div>
1 - DOT, 96MHz, 0.7V current differential pair
鈥?/div>
2 - REF, 14.318MHz
鈥?/div>
5 - PCI-Express 0.7V current differential pairs
Key Specifications:
鈥?/div>
CPU/SRC outputs cycle-cycle jitter < 85ps
鈥?/div>
PCI outputs cycle-cycle jitter < 250ps
鈥?/div>
+/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
Bit2 Bit1 Bit0
CPU
PCIEX
SRC
FSLC FSLB FSLA MHz
MHz
MHz
266.66 100.00 100.00
0
0
0
0
0
133.33 100.00 100.00
0
0
0
0
1
0
0
0
1
0
200.00 100.00 100.00
166.66 100.00 100.00
0
0
0
1
1
0
0
1
0
0
333.33 100.00 100.00
100.00 100.00 100.00
0
0
1
0
1
0
0
1
1
0
400.00 100.00 100.00
200.00 100.00 100.00
0
0
1
1
1
266.66 133.33 133.33
0
1
0
0
0
133.33 133.33 133.33
0
1
0
0
1
200.00 133.33 133.33
0
1
0
1
0
166.66 125.00 125.00
0
1
0
1
1
333.33 125.00 125.00
0
1
1
0
0
100.00 133.33 133.33
0
1
1
0
1
400.00 133.33 133.33
0
1
1
1
0
200.00 133.33 133.33
0
1
1
1
1
1
0
0
0
0
269.33 101.00 101.00
1
0
0
0
1
134.66 101.00 101.00
1
0
0
1
0
202.00 101.00 101.00
1
0
0
1
1
168.33 101.00 101.00
1
0
1
0
0
274.66 103.00 103.00
1
0
1
0
1
137.33 103.00 103.00
1
0
1
1
0
206.00 103.00 103.00
1
0
1
1
1
171.66 103.00 103.00
1
1
0
0
0
279.99 105.00 105.00
1
1
0
0
1
140.00 105.00 105.00
1
1
0
1
0
210.00 105.00 105.00
1
1
0
1
1
174.99 105.00 105.00
1
1
1
0
0
287.99 108.00 108.00
1
1
1
0
1
144.00 108.00 108.00
1
1
1
1
0
216.00 108.00 108.00
1
1
1
1
1
179.99 108.00 108.00
* Entries 00111 & 01111 are 250MHz on the B & C revision.
Bit4
Bit3
0875鈥?5/24/04
Features/Benefits:
鈥?/div>
Programmable output frequencies
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Supports tight ppm accuracy clocks for Serial-ATA
鈥?/div>
Supports spread spectrum modulation, 0 to -0.5%
down spread, 鹵0.25% center spread, and 鹵0.3%
center spread
鈥?/div>
鈥?/div>
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
Pin Configuration
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.67
33.67
33.67
33.67
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
36.00
36.00
36.00
36.00
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK_F0
FS
L
A/PCICLK_F1
FS
L
B/PCICLK_F2
VDD48
**SEL24_48#/24_48MHz
USB_48MHz
GND
DOTT_ 96MHz
DOTC_96MHz
Vtt_PwrGd#/PD
PCIEXT0
PCIEXC0
VDDPCIEX
GND
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
GND
SRCCLKT
SRCCLKC
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDPCI
PCICLK2
PCICLK1
PCICLK0
Reset#
REF0/FS
L
C
REF1
GND
X1
X2
VDDREF
SCLK
SDATA
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
IREF
GNDA
VDDA
VDDPCIEX
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
GND
56-Pin SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS954119

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