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ICS950508YFLF-T Datasheet

  • ICS950508YFLF-T

  • Programmable Timing Control HubTM for PII/IIITTM

  • 161.95KB

  • 19頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950508
Programmable Timing Control Hub鈩?for PII/III鈩?/div>
Recommended Application:
810/810E/815 and 815 B-Step type chipset
Output Features:
鈥?/div>
2 - CPUs @ 2.5V
鈥?/div>
13 - SDRAM @ 3.3V
鈥?/div>
3 - 3V66 @ 3.3V
鈥?/div>
8 - PCI @3.3V
鈥?/div>
1 - 24/48MHz@ 3.3V
鈥?/div>
1 - 48MHz @ 3.3V fixed
鈥?/div>
1 - REF @3.3V, 14.318MHz
Features/Benefits:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
CPU Output Jitter: <250ps
鈥?/div>
IOAPIC Output Jitter: <500ps
鈥?/div>
48MHz, 3V66, PCI Output Jitter: <500ps
鈥?/div>
Ref Output Jitter. <1000ps
鈥?/div>
CPU Output Skew: <175ps
鈥?/div>
PCI Output Skew: <500ps
鈥?/div>
3V66 Output Skew <175ps
鈥?/div>
For group skew timing, please refer to the
Group Timing Relationship Table.
VDDREF
X1
X2
GND
GND
3V66_0
3V66_1
3V66_2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
*FS1/PCICLK1
1
*SEL24_48#/PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GND
Vtt_PWRGD/PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GND
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4 *
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GND
GND
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GND
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND
24_48MHz/FS2*
48MHZ/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GND
1
56-Pin 300-mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
ICS950508
48MHz
24_48MHz
REF0
CPU
DIVDER
2
CPUCLK (1:0)
SDRAM
DIVDER
12
SDRAM (11:0)
SDRAM_F
FS(4:0)
PD#
SEL24_48#
Vtt_PWRGD
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
IOAPIC
PCI
DIVDER
8
PCICLK (7:0)
3V66
DIVDER
3
3V66 (2:0)
0470E鈥?4/06/05

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